1. Field of the Invention
The present invention relates to a semiconductor memory cell, specifically, a thin film transistor having an electric charge accumulating layer. The present invention also relates to a semiconductor memory device in which a thin film transistor having an electric charge accumulating layer and a thin film transistor are formed on a substrate having an insulating surface.
2. Description of the Related Art
EEPROM (Electrically Erasable and Programmable Read Only Memory) and flash memory are known as representatives of semiconductor non-volatile memories. Unlike major semiconductor memories such as DRAM (Dynamic Random Access Memory) and SRAM (static RAM), EEPROM and flash memory do not lose data when power is turned off since they are non-volatile. They are also superior to magnetic disc, which is another representative non-volatile memory, in such characteristics as high integration degree, withstandingness against impact, small power consumption, and high writing/reading speed.
Semiconductor non-volatile memories thus have characteristics suitable for portable machines, and their application to portable machines is being developed. In particular, flash memory having high integration degree is widely applied and, recently, multi-valued memories with even higher integration degree have begun to appear on the market. These are of course non-volatile memories on single crystal silicon substrates.
On the other hand, popularization of cellular phones and other portable machines having display units has brought an increasing demand for system on panel in which a display portion and a logic circuit portion are integrally formed on a substrate having an insulating surface. With this trend, techniques for manufacturing a non-volatile memory on a substrate having an insulating surface are now needed.
In manufacturing a non-volatile memory on a substrate having an insulating surface, one conceivable mode is to construct a memory cell array from semiconductor memory cells and use thin film transistors (hereinafter referred to as TFTs) for peripheral circuits such as a decoder circuit for selecting a memory cell and a writing/reading circuit.
The term semiconductor memory cell in the present invention refers to a thin film transistor that has an electric charge accumulating layer surrounded by an insulating film between a semiconductor active layer and a gate electrode. For example, the term covers a thin film transistor having a structure with a floating gate electrode, or an MNOS structure, or an MONOS structure.
For a non-volatile memory as such, important objectives are improvement in reliability of a semiconductor memory cell which is lowered as electric charges are injected to and discharged from its electric charge accumulation layer and improvement of the total operation speed of the memory cell array and the peripheral circuits.
First, regarding the reliability, a semiconductor memory cell has the following structural problem. Shown in FIGS. 2A to 2C are the structure of a typical semiconductor memory cell manufactured on a substrate having an insulating surface. FIG. 2A is a plan view thereof whereas FIGS. 2B and 2C are its sectional view in the channel length direction (sectional view of A-A′) and sectional view in the channel width direction (sectional view of B-B′), respectively. In the semiconductor memory cell of FIGS. 2A to 2C, a semiconductor active layer 202, a first gate insulating film 203, a floating gate electrode 204, a second gate insulating film 205, and a control gate electrode 206 are layered on a substrate 201 having an insulating surface. The semiconductor active layer 202 is composed of a channel region 207 and high concentration impurity regions 208 that are doped with an impurity of one conductivity type.
The floating gate electrode 204 is one mode of the electric charge accumulating layer. One of the high concentration impurity regions 208 may partially overlap the floating gate electrode 204 with the first gate insulating film 203 sandwiched therebetween.
In this semiconductor memory cell structure, what causes a problem regarding the reliability is the shape of a semiconductor active layer end 209. With the semiconductor active layer shaped as shown in FIGS. 2A to 2C, the electric field concentrates on a corner of the semiconductor active layer end when the control gate electrode and the active layer have different electric potentials. This causes local injection/discharge of electric charges in the semiconductor active layer end 209. As a result, the first gate insulating film is degraded intensively in the semiconductor active layer end 209 and the reliability is lowered.
In order to prevent local degradation of the first gate insulating film due to the electric field concentration, it is effective to invent a semiconductor memory cell structure that does not have a region where the electric field concentrates as the semiconductor active layer end 209.
As to improvement of the memory operation speed, it is important to manufacture high performance TFTs and semiconductor memory cells on a substrate having an insulating surface.
The technology of forming a TFTs on a substrate having an insulating surface has made great advances mainly through research and development of semiconductor display devices (typically, liquid crystal display devices and EL display devices). For instance, TFTs using polycrystalline silicon films have higher field effect mobility (also called mobility) than TFTs formed from amorphous silicon films and thus have enabled a driving circuit on the same substrate where pixels are formed to control a display portion, which in the past was performed by a driving circuit external to the substrate.
With system on panel looming on horizon, the operation speed has to be increased even more and TFTs of higher performance are demanded.
One of techniques for forming a TFT on a substrate having an insulating surface that has been attracting attention in recent years is manufacture of a crystalline semiconductor film by laser light irradiation. For laser oscillation apparatus, gas lasers, typically an excimer laser, and solid-state lasers, typically a YAG laser, are usually used. A technique has been disclosed in JP 2001-144027 A in which solid-state laser oscillation apparatus such as a Nd:YVO4 laser is used to irradiate an amorphous semiconductor film with laser light that is its second harmonic, and a crystalline semiconductor film larger in grain size than conventional ones is formed and used to manufacture a TFT.
However, when an amorphous semiconductor film formed on a flat surface is crystallized by laser light irradiation, the crystal obtained is polycrystal and it is impossible to control neither positions where grain boundaries containing crystal defects are formed nor positions of distortion and cracks caused by volume shrinkage of the semiconductor film, thermal stress with the base, and lattice mismatch which are brought by crystallization.
Therefore, the crystallinity of the channel region of the TFT cannot be controlled and, in the end, the grain boundaries and crystal defects included in the channel region lead to fluctuation in element characteristic between TFTs.
In short, when using laser light irradiation to form a crystalline semiconductor film, the important objective is to control the crystallinity of a channel region of a TFT by controlling positions of grain boundaries.
To attain a high speed operation memory, it is important to improve semiconductor memory cell characteristics as well as TFT characteristics. This is because improvement in TFT characteristics raise the operation speed of peripheral circuits whereas improvement in semiconductor memory cell characteristics enhances drive performance of semiconductor memory cells, thereby increasing the reading speed.